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Resource management via type inference in a hardware compiler

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Geometry of Synthesis is a technique for compiling higher-level programming languages into digital circuits via their game semantic model. Previous work presented the key idea and a provably correct compiler into asynchronous circuits in the context of the language Syntactic Control of Interference (SCI), an affine typed version of Reynolds’s Idealized Algol. Affine typing has the dual benefits of ruling out race conditions through the type system and having a finite-state game-semantic model for any term, which leads to a natural circuit representation and simpler correctness proofs. In this paper we go beyond SCI to full Idealized Algol, enhanced with shared-memory concurrency and semaphores.

Compiling ICA proceeds in three stages. First, an intermediate type system called Syntactic Control of Concurrency is used to statically determine ``concurrency bounds’’ on all identifiers in the program. Then, a program transformation is applied to the program to translate it into an equivalent SCC program in which all concurrency bounds are set to the unit. Finally, the resulting program can be then compiled into asynchronous circuits using a slightly enhanced version of the GoS II compiler, which can handle assignable variables used in non-sequential contexts.

[Paper to appear in POPL 2011 ]

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