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From game semantics to delay-insensitive circuits

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If you have a question about this talk, please contact Dan Ghica.

This work extends previous work on the compilation of higher-order imperative languages into digital circuit. We introduce concurrency, an essential feature in the context of hardware compilation and we re-use an existing game model to simplify correctness proofs. The target designs we compile to are asynchronous event-logic circuits, which naturally match the asynchronous game model of the language.

To appear at MFPS XXVI .

This talk is part of the Lab Lunch series.

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